1. Field of the Invention
The present invention relates to an integrated circuit for an optical encoder, comprising a signal processing section for generating a position detection signal from a detection signal of a light receiving element, and more particularly to an integrated circuit comprising a power source potential layer whose potential is pulled up to power source potential so as to prevent light from entering the signal processing section from a lateral direction.
2. Description of Related Art
Optical encoders and integrated circuits for signal processing as described herein are used, for example, as position detection means for a printer head. An example structure and operation will generally be described with reference to the drawings.
FIG. 1 schematically shows a structure of a position detection mechanism 12 of a printer head, including an integration circuit for optical encoder 10. As shown in FIG. 1, the position detection mechanism 12 includes a light source 14, a scaler 16, a light receiving element array 18, and a signal processing circuit 20. The belt-like scaler 16, which is movable in the directions of arrows in accordance with the movement of a printer head (not shown), alternately includes, for example, a light transmitting section (slit) 22 and a light blocking section 23, which are equally spaced along the longitudinal direction. The light source 14, the scalar 16, and the light receiving element array 18 are positioned such that light from the light source 14 passes through the light transmitting section 22 to the light receiving element array 18 but is blocked by the light blocking section 24. As shown in FIG. 1, the light receiving element array 18 and the signal processing circuit 20 are integrated into an integrated circuit 10.
FIG. 2 is a plan view (top view) schematically showing structures of the light receiving element array 18 and the signal processing circuit 20, and FIG. 3 schematically shows a structure of the signal processing circuit 20 for generating a position detection signal based on a detection signal from the light receiving element array 18 of FIG. 2. In the example shown in FIG. 2, the light receiving element array 18 comprises light receiving elements (photo diodes, for example) 26a, 26b, which belong to a plurality of groups (though only two groups are shown in FIG. 2), and these light receiving elements (namely, light receiving elements 26a of the first group and light receiving elements 26b of the second group) are alternately arranged in a line along the moving direction of the scaler 16. As shown in FIG. 3, signals output from the light receiving elements 26a and 26b of the first and second groups are then amplified by amplifiers 28a and 28b, respectively, and outputs from the amplifiers 28a and 28b are compared in a comparator 30. The signal generating circuit 20 then generates a position detection signal based on the comparison result output by the comparator 30.
FIG. 4(a) is an explanatory view showing an example of a position detection signal generated by the position detection mechanism 12, specifically an output of the signal processing circuit 20, in association with the structure of the scaler 16. As shown in FIG. 4(a), an example position detection signal rises to a high level (H) when the light transmitting section of the scaler 16 transmits light and drops to a low level (L) when light blocking section of the scaler 16 blocks light. From the number of pulses and phases of the position detection signal can be found the position to which the printer head has moved relative to the original point and its rate of movement.
In some cases, however, ringing noise as shown in FIG. 4(b) is mixed in the position detection signal generated by the position detection mechanism 12. In researching this noise, the present inventor has found that one factor contributing to such ringing noise is power source noise entering from the region where the light receiving element array 18 is electrically connected to the signal processing circuit 20. This will be described in detail with reference to the drawings.
As shown in FIG. 2, a power source potential layer 32 is provided along the periphery of the signal processing circuit so as to reduce light entering the circuit from the lateral direction. The power source potential layer 32 is a belt-like layer (a layer having a nature similar to that of a conductor formed by epitaxial growing) formed on a substrate, and the potential of the power source potential layer 32 is pulled up to power source potential (namely, power source potential is applied to the power source potential layer 32 by connecting the power source potential layer to the power source via a resistor). The entire top surface of the signal processing circuit 20 is covered with a light shielding layer so as to reduce light entering the circuit from above.
FIG. 5 is an enlarged plan view showing the boundary region L of the signal processing circuit 20 on the side of the light receiving element array 18, and FIG. 6 is a cross sectional view taken along line A—A of FIG. 5. As is clearly shown in these drawings, in the region L, a connection line 34 which electrically connects each light receiving element 26a, 26b with the interior of the signal processing circuit 20 is formed to have a multilayer structure. More specifically, the connection line 34 includes a first conductive layer 36 connected to each light receiving element 26a, 26b, a second conductive layer 38 connecting each group of the first conductive layers 36, and a through hole 40 connecting these two conductive layers 36 and 38. Thus, by forming the first conductive layer 36 and the second conductive layer 38 as different layers located at different heights to achieve a three dimensional layout, the connection lines 34 are separated for each group. Further, in the region L, both the first conductive layer 36 and the second conductive layer 38 are formed above the power source potential layer 32. These layers may be separated by an insulating layer as necessary. FIG. 5 does not show an insulating layer in order to simplify the drawing.
As shown in FIG. 6, on the substrate 42, the power source potential layer 32, an insulating layer (such as SiO2) 44, the first conductive layer 36, an insulating layer (such as SiO2) 46, the second conductive layer 38, an insulating layer (such as SiO2) 48, the light shielding metal layer 50, and an insulating layer (such as SiO2) 52 are sequentially formed in this order using a known manufacturing process. The present inventors have recognized that, with such a structure, the fact that the first conductive layer 36 and the power source potential layer 32 are located at a relatively small distance with only the insulating layer 44 being interposed between them contributes to the problem of noise. Specifically, in such a structure, power source noise is transported from the power source potential layer 32 to the first conductive layer 36, where the noise is superimposed on a detection signal supplied from the light receiving element 26a, 26b. Further, because the amplifiers 28a, 28b within the signal processing circuit 20 are high-gain amplifiers, even a small noise mixed in these amplifiers is amplified to a significant degree.